1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and more particularly, to a multi-chip package (MCP), system and a test method thereof.
2. Description of the Related Art
Mobile applications such as PDA (Personal Digital Assistant), third-generation mobile phone, and digital still camera applications require miniaturization. Generally, satisfactory miniaturization has been achieved through the use of submicron semiconductor fabrication technologies. However, continuous demand for ever increasing miniaturization has tested the limits of existing submicron technologies resulting in extended development periods and increased manufacturing costs.
To address these limitations, especially for mobile applications, a Multi-Chip Package (MCP) technology has been introduced allowing a variety of semiconductor chips, such as a NOR flash memory, a NAND flash memory, an SRAM, and a UtRAM to be mounted in a single package. Generally, MCPs with a stack of four or more semiconductor chips are known. By employing MCP technology, the internal mounting area can be reduced by 50% or more and the line structure can be simplified as compared to using a plurality of single packages. Thus, MCP technology can reduce the cost of products and increase productivity significantly.
However, due to the use of many chips, a large number of pins exist in an MCP product that can obstruct manufacturing of the product. For reducing the number of pins, the semiconductor chips included in a single MCP can be configured to share command pins.
Referring to FIG. 1A a conventional MCP is provided including a plurality of semiconductor chips CHIP_A and CHIP_B mounted in a single package. Each of the semiconductor chips CHIP_A and CHIP_B includes a plurality of command pins COMMAND PINs and a plurality of data pins DATA I/O PINs. The data pins DATA I/O PINs are individually provided for each of the semiconductor chips CHIP_A and CHIP_B, while the command pins COMMAND PINs are shared by the semiconductor chips CHIP_A and CHIP_B.
FIG. 1B is a circuit diagram of a data input buffer included in each of the semiconductor chips CHIP_A and CHIP_B shown in FIG. 1A.
Referring to FIG. 1B, the data input buffer includes two pull-up PMOS transistors and two pull-down NMOS transistors. When a buffer enable signal BUFEN, which is generated by decoding commands inputted through command pins, is activated, the data input buffer buffers external data DATA inputted through a data pin and outputs the buffered data as internal data DATA_INT.
When a test operation is performed on the MCP, each of semiconductor chips CHIP_A and CHIP_B included the MCP is respectively targeted. However, since the command pins are shared, the semiconductor chips CHIP_A and CHIP_B cannot be independently tested. After all of the semiconductor chips CHIP_A and CHIP_B enter a test mode, a test operation is performed in response to the same command. Thus, there is a need for a new method capable of independently testing the semiconductor chips included in an MCP without having an influence on the entire area of the MCP.